What is I2C?
I2C is an acronym of Inter-IC or Inter-Integrated Circuit designed by Philips in the early '80s. This bus allows easy communication between multiple modules (IC). Like Serial Peripheral Interface (SPI), this protocol just serves in short distance communications within a single device. This communication only requires two wires (sometimes called Two Wire Interface) to exchange data or information, like Asynchronous Serial Interface (RS-232 or UART's).
I2C is a simple, low bandwidth, short-distance protocol (about 2 meters) with standard clock speed up to 100kHz. But in Fast mode, I2C can reach 400kHz and 3.4MHz in High-Speed mode. Most of the modules can operate up to 100kHz. If we force it up to 1MHz, there will be a uS (micro-second) delay between transferring process.
| I2C Speed Mode | Speed (Hz) | Distance (meter) |
| Standard Speed | 100k | 2 |
| Fast Mode | 400k | 100 |
| High-Speed | 3.4M | 0.5 |
The Physical of I2C
Physically I2C bus can be seen in two wires called SCL and SDA. SCL is the clock line is used to synchronize all data transfers over I2C bus. SDA is the data line. Both SCL and SDA lines are "open drain" drivers or the chip only can drive the output low and cannot drive it high. To be able to go high, we must provide pull-up resistor (usually above 1000 ohm) to the voltage source.
If we don't provide these pull-up resistor, these two lines (SCL and SDA) will always on low logic, about nearby 0V, and these line won't work well. If you buy an I2C module such as HMCL5883L or BMP180 and read the datasheet carefully, the datasheet usually mentions the requirement pull-up resistor to be attached.
Master and Slaves
The I2C bus communication must, at least, has two devices or more, one device as master and the other as slaves. The master is always the device that drives the SCL clock line and the slaves are the devices that respond to the master. Only master device can initiate the transfer process. I2C is a half-duplex serial transmission and the data flow only in a direction at a time. the data transfer rate of this bus depends on crystal frequency of slave devices. the rate of data transfer refers to the clock frequency of SCL bus must be 1/16th of slave frequency.
Addressing
I2C is multi-point protocol. There can be more than two slaves in a line, but normally there is only one master. To distinguish one slave to another, each slave device has their unique address.
All I2C addresses are either 7 bits or 10 bits. But the common address will have 7-bit addresses. So, the I2C can control up to 128 slaves in a line with one master. There is an extra bit or eighth bit that is used to inform the slave if the master is writing or reading from it.
Start and Stop Condition
There are two conditions needed to communicate between I2C devices, START and STOP condition. START and STOP condition are two special sequence defined for I2C bus. These two conditions are defined by the master side. Both condition is signed by high logic of SCL. The different is START condition is the SDA logic transition from high to low and STOP condition is when SDA in transition from low to high.
After the START condition the bus is considered as busy and the data can be used by master after STOP condition is detected. After that the master can re-initiate the START condition to get the data and then send STOP condition to use the data, and soon. The START condition usually followed by the slave I2C address.
Exchange Data Procedure
The first thing before the data transaction is that the master begins the communication by initiating the START condition followed by sending the 7-bit unique slave device address. The address is started with the Most Significant Bit (MSB). Continue to the next extra bit (eighth bit) to determine the device status, READ or WRITE, by logic low (0) and high (1). The slave that matches with the address will continue with the transaction, any other will ignore the transaction and wait for the next.
The logic low (0) means that the status of the master is on WRITE or the slave is on receive status. The other side, the high logic (1), determine the master is on READ or the slave is on transmit status. This is followed by an ACK bit issued by the receiver to acknowledge the receipt of previous byte. Then master must now send the byte of internal register address inside the slave that it wishes to read or write. At the end of byte, the receiver issues a new ACK bit. For every 8 bit of data, the receiver sends the ACK bit. The master can continue to send data bytes to the slave and this will normally be placed in the following register because slave will automatically increment the internal register address after each byte. This sequence pattern is repeated if there is more byte needed to be transferred.
In WRITE procedure, logic low (0), when the master is done transmitting all of the data bytes it wants to send, it issues the last ACK then starting the STOP condition. In READ procedure, logic high (1), the master acknowledge the final byte it receives. This will tells the slave that its transmission is done. Then the master sends the STOP condition.
Sequences
So generally, we have the conclusion of the communication procedure to get the data from the slave device.
- Send the START condition
- Send the unique 7-bit slave I2C address with extra Write bit
- Send internal register address where we want to read from
- Send repeat START condition
- Send the unique 7-bit slave I2C address with extra Write bit
- Receive data from slave device
- Send STOP condition
How To Deal With I2C Device
The key how to deal with I2C devices is "have the device datasheet near you". This means that we must read carefully and understand the device datasheet. Because each I2C device has unique way how to deal with and different between one to another. As example, the way you deal with HMC5883L is totally different with BMP180. Each device has their own way to be deal. So, if we want to make a communication between our microcontroller and I2C device, make sure you read and understand the datasheet first.
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